Mobile robot on a factory floor
LICENSABLE EDGE AI SILICON IPPARAMETERIZED RTL

DeepNPU™
Low-Bit AI Acceleration, Hardened for the Edge

A scalable NPU IP architecture for CNN, LLM and VLA inference — configurable from 1,024 to 16,384 MACs, with INT8 / INT4 datapaths and support for 22–180 nm process nodes.

2.5–39.3
TOPS · scalable configurations
INT8 / INT4
Low-bit weights, FP32 accumulation
22–180 nm
Mature-node compatible, any foundry
1–3 months
Model to RTL, down from 1.5 years
Why DeepNPU

Transformer-class AI inside an edge power budget

Edge SoCs need LLM and VLA capability without a leading-edge node. DeepNPU is designed around the constraints that matter in deployed edge silicon: compute efficiency, data movement, integration simplicity and mature-node economics.

Hardened, not runtime-bound

Target model execution can be mapped into dedicated RTL, reducing dependence on a runtime compiler stack on the deployed SoC.

Low-bit by design

INT4 weights halve memory traffic against INT8. Accuracy stays above 99% of baseline.

One architecture, multiple sizes

Scale the same architectural foundation from compact 1K-class vision designs to 16K-class robotic configurations.

Mature-node friendly

Parameterised standard-cell RTL enables deployment across a broad 22–180 nm process range, subject to implementation targets.

CORE TECHNOLOGY · ALGORITHM HARDENING™

From trained model to silicon — with inference execution hardened in hardware.

DeepMentor’s approach separates the optimization of the AI workload from the runtime execution path. The public product story is simple: optimize the model, harden the execution, then integrate the resulting IP into the SoC.

Conventional NPU flow~18 months to market
CPU issues DMA commands step-by-step; decode latency and branch mispredictions cause continuous PE array bubbles.
Trained model
Graph compiler
SDK + runtime
Driver + firmware
Programmable NPU
DeepMentor hardening flow1–3 months to market
Dedicated FSM generates addresses autonomously; multi-dimensional data streams keep every MAC unit active.
Trained model
Miniaturisation · INT8 / INT4
Hardening · model → RTL
Silicon, 22–180 nm
COMPUTE UTILIZATION
Conventional design18.4% Peak
DeepMentor hardening>90% Peak
−90%
Data movement and operation complexity, through patented model miniaturisation.
>99%
Accuracy retained after quantisation to INT8 / INT4 weights.
SOC MICROARCHITECTURE

A clean coprocessor block on your SoC

DeepNPU decouples heavy AI execution from the host CPU cluster with lightweight control and dedicated data movement.

Host CPU
Arm / RISC-V host triggers workloads through a lightweight control boundary
Coproc IF
5 ops
DeepNPU™ core
up to 16,384 MAC
Inference
CNN · LLM · VLA
6D DMA / FSM
Hardware-managed multidimensional tensor movement keeps the compute path fed
Systolic PE arrayComputing

Share pool SRAM
Up to 2 MB on-chip scratchpad with banked paths matched to array access
Systolic GEMM
Parameterized matrix engine for A8B4 / A8B8 style low-bit inference
AXI
512-bit
SoC memory
DDR / LPDDR
01
Set

One kernel descriptor, written in a single coprocessor operation.

02
Start

Tiles stream into SRAM while the array computes. No MMIO polling loop.

03
Wait

Accumulation and activation finish in place. The next descriptor is already queued.

Scalable performance

1K to 16K MACs.
Sized for your workload.

Select the same architectural foundation at the scale that matches your application, model size and silicon budget.

Configuration1.2 GHz · Peak TOPS
Architectural peak at the stated clock. Achieved throughput depends on layer shape and memory bandwidth.
DeepNPU-16KROBOTIC
39.3
TOPS · INT8 × INT4
19.7
TOPS · INT8 × INT8
16,384
MAC units
CNN · LLM · VLA
Model classes
Typical targets
AMRs, drones and manipulators running 7B–27B VLA models on the platform.
Workloads

CNN, LLM and VLA on one GEMM engine

CNN
Computer Vision

Detection, segmentation and classification for smart cameras, inspection and machine perception.

YOLO
ResNet
U-Net
LLM
On-device Language AI

On-device assistants and instruction parsing with no cloud round trip.

7B
13B
27B
VLA
Vision-language-action

Multimodal inference for autonomous machines where perception and action must stay close to the device.

Robotics
Drones
AMR
Process compatibility

Edge AI on the nodes you already own

Miniaturised models need less logic and less SRAM. That makes mature nodes viable — with lower mask cost and proven supply.

22 nmFD-SOI / bulk
28 nmHPC / LP
40 nmLP
55 nmLP / ULP
65 nmLP
90 nmGeneric
110 nmGeneric
130 nmBCD / mixed
180 nmGeneric
Advanced matureLegacy mature
Foundry-agnostic
Standard-cell RTL. No hard macros tied to one fab.
Lower NRE
Mature-node masks and MPW shuttles keep tape-out cost low.
Long-life supply
Suited to industrial and automotive lifecycles.
Applications

Built for machines that can't wait for the cloud

Autonomous mobile robot
Logistics · RoboticsVLA · CNN
Autonomous mobile robots
Navigation, obstacle response and pick instructions from one on-board model.
Inspection drone
Aerospace · UAVCNN · LLM
Industrial drones
On-board detection, tracking and inspection workloads where latency, bandwidth and power matter.
Robot arm placing a chip on a circuit board
Embodied AIVLA
Robotic manipulation
Multimodal inference for language-guided perception and action inside industrial robotic cells.
Smart cameras
Industrial inspection
Edge AI gateways
Specifications

DeepNPU™ at a glance

Public architecture metrics are summarized below. Detailed implementation and integration documentation can be provided during technical evaluation.

Peak throughput
2.5–39.3 TOPS
INT8 × INT4 at 1.2 GHz; half rate at INT8 × INT8
Compute array
1,024–16,384 MAC
Parameterized systolic, weight-stationary architecture
Precision
INT8 / INT4
FP32 accumulation · FP32 / BF16 output
Model support
CNN · LLM · VLA
LLM / VLA up to 27B parameters on 16K
Memory interface
AXI, 512-bit
Dedicated NPU port, clear of the CPU cluster
Control interface
Coprocessor IF
RISC-V or Arm host · MMIO map for bring-up
On-chip SRAM
Up to 2 MB
Banked Share Pool; configuration-dependent
Process nodes
22–180 nm
Standard-cell, parameterized RTL; implementation dependent
Delivery
SystemVerilog RTL
Synthesizable, parameterized soft IP
WHAT SHIPS WITH YOUR DEEPNPU™ LICENCE

Everything you need from RTL to first silicon

Synthesisable RTL
Parameterised SystemVerilog with synthesis and lint constraints.
Verification package
Directed and randomised testbenches with full regression.
Bit-accurate golden model
C reference for co-simulation and silicon bring-up.
Model miniaturisation
Quantisation to INT8 / INT4 and few-shot retraining.
Algorithm Hardening™
Map target execution into dedicated RTL for the selected architecture.
SoC Integration support
Interconnect, clocking and memory-path guidance.
01EvaluateShare model, node and power target.
02ConfigureArray size and SRAM sized to the workload.
03HardenModel converted and verified as RTL.
04Tape outIntegration support through first silicon.

Size DeepNPU™ for your next tape-out

Send your target model, process node and power budget. DeepMentor can discuss configuration options, expected PPA targets and the appropriate technical package.

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